1. Field of the Invention
The present invention relates to a radiation image pick-up device and a radiation image pick-up method which can be suitably used in medical diagnoses and industrial non-destructive inspections. Radiations in the context of this specification include the X-ray, γ-ray, α-ray and β-ray.
2. Related Background Art
X-ray photographing systems conventionally installed in hospitals and elsewhere use either one of two systems, the film photographing system by which a film is exposed to X-rays irradiating and transmitted by a patient and the image processing system by which X-rays transmitted by a patient are converted into electric signals and subjected to digital image processing.
One of the available devices for realizing an image processing system is a radiation image pick-up device equipped with a phosphor for converting X-rays into visible light and a photoelectric conversion device for converting visible light into electric signals. The X-rays transmitted by a patient irradiate the phosphor, and internal information on the patient's body converted by the phosphor into visible light is supplied by the photoelectric conversion device as electric signals. If the internal information on the patient's body is converted into electric signals, those electric signals can be converted by an A/D converter into digital signals, enabling X-ray image information to be recorded, displayed, printed or used in diagnosis to be handled as digital values.
Recently, a radiation image pick-up device using an amorphous silicon semiconductor film for the photoelectric conversion device has come into practical use.
FIG. 10 shows a plan of a conventional photoelectric conversion substrate using amorphous silicon semiconductor films as materials for an MIS type photoelectric conversion element and a switching element, described in the Japanese Patent Application Laid-Open No. H08-116044, and the illustration includes wiring for connecting them.
FIG. 11 shows a section cut along line 11—11 in FIG. 10. In the following description, the MIS type photoelectric conversion element will be referred to merely as photoelectric conversion element for the sake of simplicity.
As shown in FIG. 11, photoelectric conversion elements 101 and switching elements 102 (amorphous silicon TFTs, hereinafter referred to simply as TFTs) are formed over the same substrate 103. The lower electrodes of the photoelectric conversion elements 101 are formed of the same first metallic film layer 104 as the lower electrodes (gate electrodes) of the TFTs 102, and the upper electrodes of the photoelectric conversion elements 102 are formed of the same second metallic film layer 105 as the upper electrodes (source electrodes and drain electrodes) of the TFTs 102.
The first and second metallic film layers 104 and 105 are also formed in and shared by gate drive wirings 106 and matrix signal wirings 107 within a photoelectric conversion circuit section (radiation detecting circuit section) shown in FIG. 10. An equivalent of 2×2=4 pixels is shown in FIG. 10, wherein hatched parts are light receiving faces of the photoelectric conversion elements 101. Reference numeral 109 denotes power supply lines which bias the photoelectric conversion elements, and 110, contact holes for connecting the photoelectric conversion elements 101 and the TFTs 102.
The use of the configuration having an amorphous silicon semiconductor as the main material as shown in FIG. 10 enables the photoelectric conversion elements 101, switching elements 102, gate drive wirings 106 and matrix signal wirings 107 to be fabricated over the same substrate at the same time, and thereby makes it possible to provide a photoelectric conversion circuit section (radiation detecting circuit section) of a large area easily and, moreover, at low cost.
Next will be described the device operations of the photoelectric conversion elements 101 with reference to FIGS. 12A to 12C.
FIGS. 12A to 12C are energy band diagrams illustrating the device operations of the photoelectric conversion elements 101 shown in FIG. 10 and FIG. 11.
FIGS. 12A and 12B show operations in a refresh mode and a photoelectric conversion mode, respectively, wherein the horizontal axis represents the state of each layer shown in FIG. 11 in the direction of its film thickness. Here, M1 denotes a lower electrode (G electrode) formed of the first metallic film layer 104, which may consist of Cr for instance. An amorphous silicon nitride (a-SiNx) insulating thin film layer 111 is an insulating layer stopping the passage of both electrons and holes. It requires a sufficient thickness not to give rise to a tunnel effect, and is usually formed to a thickness of 50 nm or more.
An amorphous silicon hydride (a-Si:H) thin film layer 112 is a photoelectric conversion semiconductor layer formed of an intrinsic semiconductor layer (i layer) deliberately not doped with a dopant. An N+ layer 113 is an injection stopping layer of a single conduction type carrier consisting of a non-single crystal semiconductor, such as an N-type amorphous silicon hydride thin film layer, formed to stop injection of holes into the amorphous silicon hydride thin film layer 112. M2 denotes an upper electrode (D electrode) formed of the second metallic thin film layer 105 of Al for instance.
Although the D electrode, which is the upper electrode, does not fully cover the N+ layer 113 in FIG. 10, the D electrode and the N+ layer 113 are always at the same potential because electrons freely move back and forth between the D electrode and the N+ layer 113, and the following description will presuppose this.
The device operations of the photoelectric conversion element 101 comprise two modes of operation including the refresh mode and the photoelectric conversion mode, differing with the way in which voltages are applied to the D electrode and the G electrode.
In the refresh mode shown in FIG. 12A, the negative potential is given to the D electrode relative to the G electrode, and holes, represented by black circles in the diagram, in the i layer 112 are guided to the D electrode by an electric field. At the same time, electrons, represented by white circles in the diagram, are injected into the i layer 112. In this process, some of the holes and electrons are recombined in the N+ layer 113 and in the i layer 112, and disappear. If this state stays on long enough, the holes will be swept out of the i layer 112.
In order to shift from the above-described state to the photoelectric conversion mode shown in FIG. 12B, the D electrode is provided with a positive potential relative to the G electrode. This causes electrons in the i layer 112 to be instantaneously guided to the D electrode. However, holes are not guided to the i layer 112 because the N+ layer 113 functions as the injection stopping layer for them. When light comes incident on the i layer 112 in this state, light is absorbed to give rise to electron-hole pairs. These electrons are guided by an electric field to the D electrode. On the other hand, the holes move within the i layer 112 and reach the interface between the i layer 112 and the amorphous silicon nitride insulating thin film layer 111, but they remain within the i layer 112 because they cannot move into this insulating layer 111. Then, as the electrodes move to the D electrode and the holes move to the interface of the i layer 112 with the insulating layer, a current flows from the G electrode to keep the electric neutrality within the photoelectric conversion element 101. This current, since it matches the electron-hole pairs generated by light, is proportional to the incident light.
When the refresh mode shown in FIG. 12A is resumed after the state in the photoelectric conversion mode of FIG. 12B is maintained for some time, holes staying in the i layer 112 are guided to the D electrode as described above, and a current matching these holes flows. The quantity of these holes matches the total quantity of light having come incident during the period in the photoelectric conversion mode. Then a current matching the quantity of electrons injected into the i layer 112 also flows, but this quantity can be subtracted in detection because it is substantially constant. In other words, this photoelectric conversion element 101 can detect not only the quantity of light coming incident on a real time basis but also the total quantity of light having come incident during a certain period of time.
However, if the duration of the photoelectric conversion mode becomes unusually long or the illuminance of the incident light is unusually intense for some reason or other, a current may fail to flow even though light does come incident. Such a situation occurs when, as shown in FIG. 12C, many holes remain in the i layer 112 and reduce the electric field in the i layer 112, and the generated electrons are not guided and become recombined with the holes in the i layer 112. Such a state is known as the saturated state of the photoelectric conversion element 101. If the condition of light incidence varies in this state, a current may flow unstably, but if the refresh mode is resumed, the holes in the i layer 112 will be swept out, and a current proportional to the light will flow again in the next photoelectric conversion mode.
When holes in the i layer 112 are to be swept out in the refresh mode as described above, though it is ideal to sweep out all the holes, sweeping out some of the holes would still be effective and an equal current to what was described above could be obtained, involving no problem at all. Thus, it is sufficient for the saturated state of FIG. 12C to be present at the next opportunity for detection in the photoelectric conversion mode, and the potential of the G electrode relative to the D electrode in the refresh mode, the duration of the refresh mode and the characteristics of the injection stopping layer for the N+ layer 113 can then be determined.
Further in the refresh mode, the injection of electrons into the i layer 112 is not a necessary condition, and the potential of the D electrode relative to the G electrode is not always required to be negative, because, in the presence of many holes in the i layer 112, even if the potential of the D electrode relative to the G electrode is positive, the electric field in the i layer 112 works in the direction of guiding the holes toward the D electrode. Furthermore, regarding the characteristics of the N+ layer 113, which is the injection stopping layer, need not include the capability to inject electrons into the i layer 112 as a necessary condition.
FIG. 13 shows a one-pixel equivalent part of a photoelectric conversion circuit according to the prior art, whose configuration comprises a photoelectric conversion element 101 and a TFT 102.
Referring to FIG. 13, the photoelectric conversion element 101 contains a capacitance content Ci consisting of the i layer and another capacitance content CSiN consisting of the injection stopping layer. The junction point between the i layer and an injection stopping layer (node N in FIG. 13) can no longer allow hole carriers to accumulate in the N portion when the photoelectric conversion element 101 becomes saturated, namely when there is no (or little) electric field between the D electrode and the node N (i layer), because optically generated electrons and holes are then recombined.
In other words, the potential of the node N never becomes higher than that of the D electrode. To materialize the operations in this saturated state, a diode (D1) is connected in parallel to the capacitance content Ci in the configuration shown in FIG. 13. Thus, the photoelectric conversion element 101 has three constituent elements including the capacitance content Ci, the capacitance content CSiN and the diode D1.
FIG. 14 is a time chart showing the operations in the one-pixel equivalent part of the photoelectric conversion circuit shown in FIG. 13. The circuit operations of the pixel comprising the photoelectric conversion element 101 and the TFT 102 will be described below with reference to FIG. 13 and FIG. 14.
First, the refresh operation will be described.
Referring to FIG. 13, Vs is set to 9 V and Vref, to 3 V. In the refresh operation, a switch SW-A is turned to Vref, a switch SW-B to Vg (on) and a switch SW-C on. By achieving this state, the D electrode is biased to Vref (6V), the G electrode to a GND potential, and the node N to the maximum Vref (6V). The maximum in this context means that, if the potential of the node N was already accumulated to or above Vref by the photoelectric conversion operation before this refresh operation, the node N will be biased to Vref via the diode D1. On the other hand, if the prior photoelectric conversion did not raise the potential of the node N to any more than Vref, the node N will not be biased to the potential of Vref by this refresh operation. In actual use, if operations had been done a plurality of times in the past, the node N can be assumed to be virtually biased to Vref (6V) by this refresh operation.
Then, after the node N is biased to Vref, the switch SW-A is turned to the Vs side. This causes the D electrode to be biased to Vs (9V). By this refresh operation, hole carriers accumulated in the node N of the photoelectric conversion element 101 are swept away toward the D electrode.
Next, the period of irradiation with X-rays will be described.
As shown in FIG. 14, X-rays are radiated in a pulse form. The X-rays transmitted by the subject irradiate a phosphor F1 and are converted into visible light. The visible light from the phosphor F1 irradiates a semiconductor layer (i layer), and undergoes photoelectric conversion. Hole carriers generated by the photoelectric conversion are accumulated in the node N and raise its potential. As the TFT 102 in an off state, the potential on the G electrode side is raised as much.
The wait period intervenes between the refresh period and the X-ray irradiation period. Nothing particular is done in this wait period, which is a standby period provided against the instability of the characteristics of the photoelectric conversion element 101 caused by a dark current or the like immediately after the refresh operation so as to allow no operation to take place until the instability is eased. There is no particular need for a wait period if the characteristics of the photoelectric conversion element 101 are not unstable immediately after the refresh operation.
Next, a transfer operation will be described.
In the transfer operation, the switch SW-B is turned to the Vg (on) side to turn on the TFT 102. This causes electron carriers (Se) matching the quantity of hole carriers (Sh) accumulated by irradiation with X-rays to flow from the read capacitance C2 side toward the G electrode via the TFT 102 to raise the potential of the read capacitance C2. The relationship between Se and Sh then is Se=Sh×CSiN/(CSiN+Ci). The potential of the read capacitance C2 is at the same time amplified by an amplifier and outputted. The TFT 102 is kept on for a long enough period to allow sufficient signal charges to be transferred, and then turned off.
Finally, a reset operation will be described.
In the reset operation, the switch SW-C is turned on and the read capacitance C2 is reset to the GND potential to prepare for the next transfer operation.
FIG. 15 is a two-dimensional circuit diagram of a conventional photoelectric conversion device.
For the sake of simplifying the illustration, only an equivalent of 3×3=9 pixels is shown in FIG. 15. Reference signs S1-1 through S3-3 denote photoelectric conversion elements; T1-1 through T3-3, switching elements (TFTs); G1 through G3, gate wirings for turning on and off the TFTs (T1-1 through T3-3); M1 through M3, signal wirings; and Vs-line, a wiring for providing an accumulated bias or a refresh bias to the photoelectric conversion elements (S1-1 through S3-3).
Referring to FIG. 15, the electrodes on the solidly black sides of the photoelectric conversion elements (S1-1 through S3-3) are G electrodes, and those on the opposite sides are D electrodes. Whereas the D electrodes share pat of the Vs-line, thin N+ layers are used as the D electrodes for the convenience of letting light come incident. The photoelectric conversion elements (S1-1 through S3-3), the TFTs (T1-1 through T3-3), the gate wirings G1 through G3, the signal wirings M1 through M3 and the Vs-line are collectively referred to as the photoelectric conversion circuit section (radiation detecting circuit section) 701.
The Vs-line is biased by a power supply Vs or a power supply Vref, and they are switched over in response to control signals of VSC. Reference sign SR1 denotes a shift register for providing drive pulse voltages to the gate wirings G1 through G3, and voltages to turn on the TFTs (T1-1 through T3-3) are supplied from outside. The voltages to be supplied then are determined by the power supply Vg (on).
A read circuit section 702 amplifies the parallel signal outputs of the signal wirings M1 through M3 in the photoelectric conversion circuit section (radiation detecting circuit section) 701, converts them into series, and outputs the converted signals.
Reference signs RES1 through RES3 denote switches for resetting the signal wirings M1 through M3; A1 through A3, amplifiers for amplifying the signals of the signal wirings M1 through M3; CL1 through CL3, sample hold capacitances for temporarily storing the signals amplified by the amplifiers A1 through A3; Sn1 through Sn3, switches for performing sample holding; B1 through B3, buffer amplifiers; Sr1 through Sr3, switches for converting parallel signals into series; SR2, a shift register for providing the switches Sr1 through Sr3 with pulses for conversion into series; and Ab, a buffer amplifier for outputting the signals converted into series.
FIG. 16 is a time chart showing the operations in the photoelectric conversion device shown in FIG. 15. The operations of the photoelectric conversion device shown in FIG. 15 will be described below with reference to this time chart.
A control signal VSC is intended to provide two different kinds of biases to the Vs-line, namely to the D electrodes of the photoelectric conversion elements (S1-1 through S3-3). The D electrodes take on Vref (V) when the control signal VSC is “Hi” and Vs (V) when the control signal VSC is “Lo”. Both the read power supply Vs (V) and the refresh power supply Vref (V) are DC power supplies.
First, operations in the refresh period will be described.
All the signals of the shift register SR1 are set to “Hi” and a CRES signal of the read circuit section 702 is set to “Hi”. In this state, continuity is established for all the TFTs for switching use (T1-1 through T3-3) and for the switching elements RES1 through RES3 in the read circuit 702, and the G electrodes of all the photoelectric conversion elements (S1-1 through S3-3) take on the GND potential. Then, when the control signal VSC becomes “Hi”, the D electrodes of all the photoelectric conversion elements (S1-1 through S3-3) enter into a state of being biased by a refresh power supply Vref (V) (negative potential). This places all the photoelectric conversion elements (S1-1 through S3-3) in the refresh mode, and refreshing takes place.
Next, the photoelectric conversion period will be described.
When the control signal VSC switched over to a “Lo” state, the D electrodes of all the photoelectric conversion elements (S1-1 through S3-3) enter into a state of being biased by a read power supply Vs (positive potential). In this way, the photoelectric conversion elements (S1-1 through S3-3) are placed in the photoelectric conversion mode. In this state, all the signals of the shift register SR1 are turned “Lo”, and the CRES signal of the read circuit section 702 is turned “Lo”. This causes all the TFTs for switching use (T1-1 through T3-3) to be turned off, and so are the switching elements RES1 through RES3 of the read circuit 702. The G electrodes of all the photoelectric conversion elements (S1-1 through S3-3) are placed in an open state on a DC basis, but the potential is maintained because the photoelectric conversion elements (S1-1 through S3-3) also have capacitance contents among their constituent elements.
Up to this point, no electric charge is generated because no light has come incident on the photoelectric conversion elements (S1-1 through S3-3). Namely, no current flows. When the light source is turned on in a pulse form in this state, light irradiates the D electrode (N+ electrode) of each of the photoelectric conversion elements (S1-1 through S3-3), and a so-called photoelectric current flows. Though the light source is not represented in FIG. 15, it is a fluorescent lamp, an LED, a halogen lamp or the like in a copying machine for instance. In an X-ray image pick-up device, it is literally an X-ray source, and in this case a scintillator for conversion of X-rays into visible light can be used. The photoelectric current caused to flow by the light is accumulated in each of the photoelectric conversion elements (S1-1 through S3-3) as electric charges, and held even after the light source is turned off.
Next, the read period will be described.
The read operation takes in a sequence of the first row of photoelectric conversion elements (S1-1 through S1-3), then the second row of photoelectric conversion elements (S2-1 through S2-3) and finally the third row of photoelectric conversion elements (S3-1 through S3-3).
First to read out the photoelectric conversion elements (S1-1 through S1-3) of the first row, a gate pulse is given from SR1 to the gate wiring G1 of the switching element TFTs (T1-1 through T1-3). When this is done, the high level of the gate pulse is a voltage V (on) supplied from outside. The TFTs (T1-1 through T1-3) are thereby turned on, and signal charges accumulated in the photoelectric conversion elements (S1-1 through S1-3) of the first row are transferred to the signal wirings M1 through M3.
Though not represented in FIG. 15, read capacitances are added to the signal wirings M1 through M3, and signal charges are transferred to the read capacitances via the TFTs (T1-1 through T1-3). The read capacitance added to the signal wiring M1, for instance, is equivalent to the total of (three) capacitances between the gate and source electrodes (Cgs) of the TFTs (T1-1 through T3-1) connected to the signal wiring M1, and corresponds to the capacitance content C2 in FIG. 13. The signal charges transferred to the signal wirings M1 through M3 are amplified by the amplifiers A1 through A3. By turning on the CRES signal, they are transferred to the sample hold capacitances CL1 through CL3 to turn off the CRES signal, and are held.
Then, by applying pulses from the shift register SR2 in the sequence of the switches Sr1, S2 and Sr3, the signals held by the sample hold capacitances CL1 through CL3 are outputted from the amplifier Ab in the sequence of the sample hold capacitances CL1, CL2 and CL3. As a result, photoelectrically converted signals equivalent to the first row of the photoelectric conversion elements (S1-1 through S1-3) are successively read out. Signals are read out in a similar way from the photoelectric conversion elements (S2-1 through S2-3) of the second row and the photoelectric conversion elements (S3-1 through S3-3) of the third row.
By sampling signals of the signal wirings M1 through M3 with an SMPL signal of the first row and holding them into the sample hold capacitances CL1 through CL3, it is made possible to resetting the signal wirings M1 through M3 to the GND potential with the CRES signal and to apply a gate pulse to the gate wiring G2 after that. Thus, while the signals of the first row are being subjected to conversion into series by the shift register SR2, the signal charges of the photoelectric conversion elements (S2-1 through S2-3) of the second row can be transferred by the shift register SR1 at the same time.
By the operations so far described, the signal charges of all the photoelectric conversion elements (S1-1 through S3-3) from the first through third rows can be outputted.
The operations of the X-ray image pick-up device described above constitute, so to speak, a sequence to acquire one still image by performing a refresh operation, irradiating the subject with X-rays and reading out the resultant signals. Where consecutive moving images are to be acquired, the operations shown in the time chart of FIG. 16 can be repeated as many as the number of desired moving images.
However, where moving images are to be acquired with an X-ray image pick-up device using a particularly large number of pixels, a further improvement in frame frequency will be required. Where an operation to refresh photoelectric conversion elements is to be carried out via a Vs-line which is common to all the photoelectric conversion elements, it is indispensable to secure one refresh period per frame. This gives rise to a particular problem that, when moving images are to be acquired, the frame frequency is reduced, namely the operation speed slows down.
The required area and pixel pitch for simple photographing of the chest are commonly said to be not less than 40 cm square and not more than 200 μm, respectively. Supposing that an X-ray image pick-up device having a photographing area of 40 cm square and a pixel pitch of 200 μm is to be fabricated, the number of photoelectric conversion elements will be as many as four million. Refreshing so vast a number of pixels at a time would entail a correspondingly larger current flowing at the time of refreshing, the GND potential and voltage fluctuations of the power supply line of the X-ray image pick-up device would become correspondingly greater, making it impossible to pick up images stably.
Depending on the requirements of the desired images, irradiation with X-rays would have to wait for some period until these fluctuations become reduced. Though not represented in FIG. 16, the wait period in FIG. 14 corresponds to this period. In other words, refreshing a photoelectric conversion device at a time would require not only one refresh period per frame but also one wait period per frame.
As described so far, the prior art according to which all the photoelectric conversion elements are refreshed once per frame of read operation involves a problem of difficulty to photograph moving images.
Moreover, if the photographing area is as large as 40 cm square, the capacitance of the signal wirings M1 through M3 will run up to somewhere between 50 pF and 100 pF. And if the photographic pixels are arranged at a 200 μm pitch, their capacitance will be about 1 pF to 3 pF. Supposing a signal wiring capacitance of 100 pF and a pixel capacitance of 2 pF and a transfer operation is carried out via TFTs, the signal voltage will drop to 2 pF/(2 pF+100 pF)≦ 1/50 before and after that. Similarly, the noise voltage will also drop, but there also is a problem that, because the noise components in the read circuit section 702 at the later stage, including so-called circuit noises such as thermal noise of resistances and the shot noise of transistors, are not zero, the eventual S/N ratio of the system will drop.
In order to make up for this drop in system S/N ratio, the circuit noise at the initial stage of the read circuit section 702 should be reduced. More specifically, the initial stage should be composed of an amplifier embodying considerably high standards of low noise design. To realize this, the element size of the transistors constituting the amplifier will become huge, resulting in a greatly increased chip size. This would invite a greater current consumption, and lead to a secondary problem of requiring a cooling mechanism against the resultant heat emission.
One way to solve this problem of S/N ratio drop is proposed in the Japanese Patent Application Laid-Open No. H11-307756, by which signal potentials from photoelectric conversion elements are entered into the gates of TFTs, and an output is obtained by using these TFTs as source followers. This method provides an advantage in terms of S/N ratio because output signals from the photoelectric conversion elements are entered into read circuits without suffering a drop.
However, voltages due to accumulated charges in the photoelectric conversion element are applied to the gate terminals of the source follower TFTs for a long period of time. There generally is a problem that TFTs mainly made of amorphous silicon suffer fluctuations in gate threshold voltage (Vth), the indicator for turning TFTs on, due to electric field stresses working on their gate terminals.
In the circuit configuration described in the Japanese Patent Application Laid-Open No. H11-307756, relative to the gate terminal voltage Vg of the source followers due to the accumulated charges in the photoelectric conversion elements, output signals suffering a drop corresponding to the threshold voltage Vth of the TFTs, are outputted from the source terminals at this reduced level. Thus, the output signal voltage is Vg−Vth. This voltage is entered into the read circuit section. Generally, the absolute maximum rating that can be applied to the input terminal of a read circuit (IC) composed of crystalline silicon is about 0.5 V relative to its photoelectric source voltage. There is a risk that the input rating of the read circuit may be surpassed if the threshold voltage Vth in the source follower TFTs varies, and if this risk actualizes, the read circuit may be destroyed.
Semiconductor processes are becoming increasingly fine today, and they are required to be reduced in source voltage and current consumption. As the power source for read circuits, a single 5 V source is coming into increasing use. Thus, both foreign and domestic requirements for the input voltage to read circuits are often 0 to 5 V, resulting in a constraint that threshold voltage Vth fluctuations of source follower type TFTs should be restricted to an extremely narrow range. In reality, the threshold voltage Vth of TFTs is uneven even at the time of shipment from the factory (at the time of TFT fabrication), and also varies while they are being operated. The Japanese Patent Application Laid-Open No. H11-307756 makes no mention of any solution to this problem of threshold voltage Vth fluctuations in TFTs.
Further, the photoelectric conversion elements according to the Japanese Patent Application Laid-Open No. H11-307756 are formed of PIN-type photodiodes. Since these PIN-type photodiodes require no refresh operation which MIS-type photoelectric conversion elements do require, they seem to be relatively free from the problem of difficulty in moving image picking-up ensuing from the refresh operation. However, they require two kinds of junctions including PI junction and IN junction, entailing a problem of an increased dark current. Especially the P layer is a layer unique to photoelectric conversion elements, and requires a completely different fabrication process from other TFTs fabricated over the same substrate. This means a laminated structure for which TFTs and photoelectric conversion elements have to be separately fabricated, involving disadvantages in yield and cost.